As ATE test sequences become more complex and the requirements for testing units under test (UUTs) such as circuits, circuit cards, and electronic sub-systems, require more complex and finite synchronization of signals (stimulus and acquisition), ATE systems must have the ability to stimulate and measure multiple signals maintaining the temporal relationships of the signals. A typical conventional multi-core CPU which consists of two or more processors put together on a single die which shares the same interconnect to the rest of the system is called a multi-core CPU. The CPU is the heart of the computer motherboard.
Modern desktop operating systems (OS) feature multitasking operations. Multitasking operating systems allow for the concurrent execution of computer instructions. A common example is allowing a user to enter information while, perceptually at the same time, performing a data communication process to send or retrieve additional data. Multitasking achieves concurrency by performing multiple tasks over a defined time period.
Multitasking does not imply parallel execution. Each core of a multi-core central processing unit (CPU) can execute one computer instruction at a time. In a multi-core system, multiple computer instructions can be executed in parallel. Nevertheless there is no guarantee that any given instruction will have an available core at the needed time nor execute in parallel to another specific instruction.
The perception of parallel computer instruction execution occurs when the central processing unit context switches rapidly and when no individual instruction or discrete set of instructions requires more than the minimum of CPU time.
When software requests a computer instruction be performed, the responsibility for assigning the instruction to a core for execution is given to the operating system and CPU embedded firmware. The operating system assigns a priority based on criteria not necessarily consistent with the desired purpose of the requesting application. The time between when an instruction request is made by software and the moment when the instruction is performed on a core is nondeterministic. The variability of when the instruction is performed is arbitrary and presents a predicament to ATE system test program execution as the arbitrary nature of the instruction execution prevents the software from maintaining temporal relationships between the multiple computer instructions.
In modern multi-thread enabled operating systems, a thread in a process can migrate from one processor core to another processor core, with each migration reloading the processor cache. Under heavy system loads, specifying which processor should run a specific thread can improve performance by reducing the number of times the processor cache is reloaded. The association between a processor and a thread is called the processor affinity.
Synchronization of computer instructions is a common problem within parallel software execution and is a major factor preventing ATE systems from having the ability to stimulate and measure multiple signals while maintaining the temporal relationships of the signals. Therefore, it is desired to have a system in which computer instructions have improved temporal alignment. It is desired that synchronization of tasks performed in parallel be maintained as configured by the user and be consistent across multiple executions of a test program. Further, it is desired to abstract the implementation details of temporal alignment and synchronization from the user such that the user need not have specific knowledge of the underlying computer and OS architectures.
Prior art software ATE Test Executives can perform tests in parallel but fail to achieve the synchronicity of operations across a coherent time-domain set of instrument operations. Without the ability to synchronize instrument operations, temporal information cannot be extracted when comparing signals generated or acquired by parallel instrument operations. This invention relates specifically to the method and process of maintaining temporal alignment of ATE tasks by a test executive and maintaining the temporal alignment of instrument actions leading to temporal coherence of signals.